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MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. The eight latches of the HCT373A are transparent D-type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs. * Output Drive Capability: 15 LSTTL Loads * TTL/NMOS-Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 mA * In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 196 FETs or 49 Equivalent Gates
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20 PDIP-20 N SUFFIX CASE 738
1
20
MC74HCT373AN AWLYYWW 1 20
20
1
SOIC WIDE-20 DW SUFFIX CASE 751D 1 TSSOP-20 DT SUFFIX CASE 948E
HCT373A AWLYYWW 20 HCT 373A ALYW 1
20 1
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC74HCT373AN MC74HCT373ADW MC74HCT373ADT MC74HCT373ADTR2 Package PDIP-20 SOIC-WIDE TSSOP-20 TSSOP-20 Shipping 1440 / Box 38 / Rail 1000 / Reel 75 / Rail 2500 / Reel
w
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
MC74HCT373ADWR2 SOIC-WIDE
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 11
1
Publication Order Number: MC74HCT373A/D
MC74HCT373A
PIN ASSIGNMENT
OUTPUT ENABLE Q0 D0 2 5 6 9 12 15 16 19 D1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LATCH ENABLE
LOGIC DIAGRAM
3 4 7 8 13 14 17 18
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7
FUNCTION TABLE
Inputs Output Enable L L L H Latch Enable H H L X D H L X X Output Q H L No Change Z
LATCH ENABLE OUTPUT ENABLE
11 1
X = don't care Z = high impedance
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Design Criteria Value 49 Units ea. ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product 1.5 5.0 mW pJ 0.0075 *Equivalent to a two-input NAND gate.
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MC74HCT373A
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II II I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I II I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I I II I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIII I I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I IIIIIIIIIIIIIIIIIIIIIII II I I III I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I
II I IIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
VCC Vin Iin Vout Iout PD SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Lead Temperature, 1 mm from Case for 10 Seconds C 260 (Plastic DIP, SOIC, SSOP or TSSOP Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC TA Parameter
Min 4.5 0
Max 5.5
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout tr, tf
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC 500
- 55 0
+ 125
C ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85C 2.0 2.0 0.8 0.8 4.4 5.4
Symbol VIH VIL
Parameter
Test Conditions
VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
- 55 to 25C 2.0 2.0 0.8 0.8 4.4 5.4
v 125C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4
Unit V V V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 6.0 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 6.0 mA
Maximum Low-Level Input Voltage
VOH
Minimum High-Level Output Voltage
3.98 0.1 0.1
3.84 0.1 0.1
VOL
Maximum Low-Level Output Voltage
V
0.26
0.33
Iin
Maximum Input Leakage Current Maximum Three-State Leakage Current
Vin = VCC or GND
0.1 0.5
1.0 5.0
1.0 10
mA mA
IOZ
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA
ICC
Maximum Quiescent Supply Current (per Package)
5.5
4.0
40
160
mA
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MC74HCT373A
III I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
DICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA 5.5 -55C 2.9 25C to 125C 2.4 mA NOTE: 1. Total Supply Current = ICC + SDICC. NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II I I I I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Guaranteed Limit v 85C 35 40 38 44 15 10 15 Symbol tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Parameter - 55 to 25C 28 32 30 35 12 10 15 v 125C 42 48 45 53 18 10 15 Unit ns ns ns ns ns Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Input Capacitance tTLH, tTHL Cin pF pF Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Latch)* 65 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Guaranteed Limit v 85C 13 13 15 Symbol tsu th Parameter - 55 to 25C 10 10 12 v 125C 15 15 18 Unit ns ns ns ns Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time, Latch Enable to Input D (Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1) tw tr, tf 500 500 500
TIMING REQUIREMENTS (VCC = 5.0 V 10%, Input tr = tf = 6.0 ns)
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MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0 3 D Q D1 4 D Q D2 7 D Q D3 8 D Q D4 13 D Q D5 14 D Q D6 17 D Q D7 18 D Q
LE LATCH 11 ENABLE OUTPUT 1 ENABLE
LE
LE
LE
LE
LE
LE
LE
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
SWITCHING WAVEFORMS
tr INPUT D tPLH Q tTLH 2.7 V 1.3 V 0.3 V 90% 1.3 V 10% tPHL tf tw LATCH ENABLE 1.3 V tPLH Q 1.3 V tPHL 1.3 V
3V GND
3V GND
tTHL
Figure 1.
Figure 2.
OUTPUT ENABLE
3V 1.3 V tPZL tPLZ 10% tPZH tPHZ 90% GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE LATCH ENABLE INPUT D 1.3 V tsu th 1.3 V VALID
3V GND 3V GND
Q
1.3 V
Q
1.3 V
Figure 3.
Figure 4.
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MC74HCT373A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L*
TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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MC74HCT373A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
11
-A-
20 1
B
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
M
0.25 (0.010) TA
M
M
TB
M
SO-20 DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
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L
MC74HCT373A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE A
M
20X
K REF TU
0.15 (0.006) T U
S
0.10 (0.004)
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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IIII IIII IIII
SECTION N-N M DETAIL E DETAIL E
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC74HCT373A/D

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